(3 intermediate revisions by 2 users not shown) | |||
Line 8: | Line 8: | ||
<font size="4">'''The Meyer Lectures on Digital Systems Design''' </font> | <font size="4">'''The Meyer Lectures on Digital Systems Design''' </font> | ||
− | [ | + | [https://www.projectrhea.org/learning/slectures.php Slectures] by [[User:Rwayner|Robert Wayner]] |
© 2013 | © 2013 | ||
Line 32: | Line 32: | ||
<span style="color:orange"> TO BE DONE LATER </span> | <span style="color:orange"> TO BE DONE LATER </span> | ||
*[[ECE270 Slecture Wayner Digital System Design Objectives Module 2|Objectives and Outcomes]] | *[[ECE270 Slecture Wayner Digital System Design Objectives Module 2|Objectives and Outcomes]] | ||
− | |||
− | |||
([https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod2_LS_IMPACT_2013.pdf Original Notes by Prof. Meyer]) | ([https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod2_LS_IMPACT_2013.pdf Original Notes by Prof. Meyer]) | ||
Line 51: | Line 49: | ||
<span style="color:orange"> TO BE DONE LATER </span> | <span style="color:orange"> TO BE DONE LATER </span> | ||
*[[ECE270 Slecture Wayner Digital System Design Objectives Module 4|Objectives and Outcomes]] | *[[ECE270 Slecture Wayner Digital System Design Objectives Module 4|Objectives and Outcomes]] | ||
− | |||
([https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod4_LS_IMPACT_2013.pdf Original Notes by Prof. Meyer]) | ([https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod4_LS_IMPACT_2013.pdf Original Notes by Prof. Meyer]) | ||
Line 58: | Line 55: | ||
---- | ---- | ||
− | [[ | + | [[2014 Spring ECE 270 Brown|Go to ECE 270 Homepage]] |
Latest revision as of 16:38, 2 April 2014
The Meyer Lectures on Digital Systems Design
© 2013
Contents
Foreword by Robert Wayner
Module 1: Boolean Algebra & CMOS logic structures
UNDER CONSTRUCTION
Module 2: Combinational Logic Circuits & Introduction to ABEL
TO BE DONE LATER
Module 3: Sequential Logic Circuits
TO BE DONE LATER
Module 4: Computer Functional Block & Arithmetic Logic Unit
TO BE DONE LATER