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<div style="font-family: Verdana, sans-serif; font-size: 12px; text-align: justify; width: 92%; margin: auto; border: 1px solid #aaa; padding: 1em;">
 
== Module 1: Boolean Algebra &amp; CMOS logic structures ==
 
== Module 1: Boolean Algebra &amp; CMOS logic structures ==
 +
<span style="color:orange"> UNDER CONSTRUCTION </span>
 
*[[ECE270 Slecture Wayner Digital System Design Objectives Module 1|Objectives and Outcomes]]
 
*[[ECE270 Slecture Wayner Digital System Design Objectives Module 1|Objectives and Outcomes]]
 
*[[ECE270 Fall 2013 Module 1 Slecture 1|Converting integers to binary]]
 
*[[ECE270 Fall 2013 Module 1 Slecture 1|Converting integers to binary]]
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<div style="font-family: Verdana, sans-serif; font-size: 12px; text-align: justify; width: 92%; margin: auto; border: 1px solid #aaa; padding: 1em;">
 
== Module 2: Combinational Logic Circuits &amp; Introduction to ABEL  ==
 
== Module 2: Combinational Logic Circuits &amp; Introduction to ABEL  ==
<span style="color:orange"> UNDER CONSTRUCTION </span>
+
<span style="color:orange"> TO BE DONE LATER </span>
 
*[[ECE270 Slecture Wayner Digital System Design Objectives Module 2|Objectives and Outcomes]]
 
*[[ECE270 Slecture Wayner Digital System Design Objectives Module 2|Objectives and Outcomes]]
 
*[[ECE270 Fall 2013 Module 2 Slecture 1|Karnaugh Map techniques]]
 
*[[ECE270 Fall 2013 Module 2 Slecture 1|Karnaugh Map techniques]]
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<div style="font-family: Verdana, sans-serif; font-size: 12px; text-align: justify; width: 92%; margin: auto; border: 1px solid #aaa; padding: 1em;">
 
== Module 3: Sequential Logic Circuits  ==
 
== Module 3: Sequential Logic Circuits  ==
<span style="color:orange"> UNDER CONSTRUCTION </span>
+
<span style="color:orange"> TO BE DONE LATER </span>
 
*[[ECE270 Slecture Wayner Digital System Design Objectives Module 3|Objectives and Outcomes]]
 
*[[ECE270 Slecture Wayner Digital System Design Objectives Module 3|Objectives and Outcomes]]
  
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<div style="font-family: Verdana, sans-serif; font-size: 12px; text-align: justify; width: 92%; margin: auto; border: 1px solid #aaa; padding: 1em;">
 
== Module 4: Computer Functional Block &amp; Arithmetic Logic Unit  ==
 
== Module 4: Computer Functional Block &amp; Arithmetic Logic Unit  ==
<span style="color:orange"> UNDER CONSTRUCTION </span>
+
<span style="color:orange"> TO BE DONE LATER </span>
 
*[[ECE270 Slecture Wayner Digital System Design Objectives Module 4|Objectives and Outcomes]]
 
*[[ECE270 Slecture Wayner Digital System Design Objectives Module 4|Objectives and Outcomes]]
  

Revision as of 08:06, 23 August 2013


The Meyer Lectures on Digital Systems Design

Slectures by Robert Wayner

© 2013



Module 2: Combinational Logic Circuits & Introduction to ABEL

TO BE DONE LATER


(Original Notes by Prof. Meyer)


Module 3: Sequential Logic Circuits

TO BE DONE LATER

(Original Notes by Prof. Meyer)


Module 4: Computer Functional Block & Arithmetic Logic Unit

TO BE DONE LATER


(Original Notes by Prof. Meyer)



Go to ECE 270 Homepage

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To all math majors: "Mathematics is a wonderfully rich subject."

Dr. Paul Garrett