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<font size="4">'''The Brown-Meyer Lectures on Digital Systems Design''' </font>  
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<font size="4">'''The Meyer Lectures on Digital Systems Design''' </font>  
  
[[Slectures|Slectures]] by [[User:Rwayner|Robert Wayner]]  
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[https://www.projectrhea.org/learning/slectures.php Slectures] by [[User:Rwayner|Robert Wayner]]  
  
 
© 2013  
 
© 2013  
 
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</center>  
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== [[ECE270 Fall 2013 intro Slecture Digital System Design|Foreword by Robert Wayner]]==
 
== [[ECE270 Fall 2013 intro Slecture Digital System Design|Foreword by Robert Wayner]]==
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== Module 1: Boolean Algebra &amp; CMOS logic structures ==
 
== Module 1: Boolean Algebra &amp; CMOS logic structures ==
*[[ECE270 Slecture Wayner Digital System Design Objectives|Objectives and Outcomes]]
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<span style="color:orange"> UNDER CONSTRUCTION </span>
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*[[ECE270 Slecture Wayner Digital System Design Objectives Module 1|Objectives and Outcomes]]
 
*[[ECE270 Fall 2013 Module 1 Slecture 1|Converting integers to binary]]
 
*[[ECE270 Fall 2013 Module 1 Slecture 1|Converting integers to binary]]
 
*[[ECE270 Fall 2013 Module 1 Slecture 2|Using MOSFETS as logic gates]]
 
*[[ECE270 Fall 2013 Module 1 Slecture 2|Using MOSFETS as logic gates]]
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== Module 2: Combinational Logic Circuits &amp; Introduction to ABEL  ==
 
== Module 2: Combinational Logic Circuits &amp; Introduction to ABEL  ==
<span style="color:orange"> UNDER CONSTRUCTION </span>
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<span style="color:orange"> TO BE DONE LATER </span>
*Objectives and Outcomes
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*[[ECE270 Slecture Wayner Digital System Design Objectives Module 2|Objectives and Outcomes]]
*[[ECE270 Fall 2013 Module 2 Slecture 1|Karnaugh Map techniques]]
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([https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod2_LS_IMPACT_2013.pdf Original Notes by Prof. Meyer])
 
([https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod2_LS_IMPACT_2013.pdf Original Notes by Prof. Meyer])
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== Module 3: Sequential Logic Circuits  ==
 
== Module 3: Sequential Logic Circuits  ==
<span style="color:orange"> UNDER CONSTRUCTION </span>
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<span style="color:orange"> TO BE DONE LATER </span>
*Objectives and Outcomes
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*[[ECE270 Slecture Wayner Digital System Design Objectives Module 3|Objectives and Outcomes]]
  
 
([https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod3_LS_IMPACT_2013.pdf Original Notes by Prof. Meyer])
 
([https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod3_LS_IMPACT_2013.pdf Original Notes by Prof. Meyer])
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== Module 4: Computer Functional Block &amp; Arithmetic Logic Unit  ==
 
== Module 4: Computer Functional Block &amp; Arithmetic Logic Unit  ==
<span style="color:orange"> UNDER CONSTRUCTION </span>
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<span style="color:orange"> TO BE DONE LATER </span>
*Objectives and Outcomes
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*[[ECE270 Slecture Wayner Digital System Design Objectives Module 4|Objectives and Outcomes]]
 
+
  
 
([https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod4_LS_IMPACT_2013.pdf Original Notes by Prof. Meyer])
 
([https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod4_LS_IMPACT_2013.pdf Original Notes by Prof. Meyer])
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[[2013 Fall ECE 270 Brown|Go to ECE 270 Homepage]]
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[[2014 Spring ECE 270 Brown|Go to ECE 270 Homepage]]

Latest revision as of 16:38, 2 April 2014


The Meyer Lectures on Digital Systems Design

Slectures by Robert Wayner

© 2013



Module 2: Combinational Logic Circuits & Introduction to ABEL

TO BE DONE LATER

(Original Notes by Prof. Meyer)


Module 3: Sequential Logic Circuits

TO BE DONE LATER

(Original Notes by Prof. Meyer)


Module 4: Computer Functional Block & Arithmetic Logic Unit

TO BE DONE LATER

(Original Notes by Prof. Meyer)



Go to ECE 270 Homepage

Alumni Liaison

Questions/answers with a recent ECE grad

Ryne Rayburn