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| + | [[Category:digital systems]] | ||
| + | [[Category:Lecture_notes]] | ||
| + | [[Category:Slecture]] | ||
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<center><font size="4"></font> | <center><font size="4"></font> | ||
| − | <font size="4">'''The | + | <font size="4">'''The Meyer Lectures on Digital Systems Design''' </font> |
| − | [ | + | [https://www.projectrhea.org/learning/slectures.php Slectures] by [[User:Rwayner|Robert Wayner]] |
© 2013 | © 2013 | ||
</center> | </center> | ||
| − | |||
| − | [[ECE270 Fall 2013 | + | <div style="font-family: Verdana, sans-serif; font-size: 12px; text-align: justify; width: 92%; margin: auto; border: 1px solid #aaa; padding: 1em;"> |
| + | == [[ECE270 Fall 2013 intro Slecture Digital System Design|Foreword by Robert Wayner]]== | ||
| + | </div> | ||
| + | <br> | ||
| + | <div style="font-family: Verdana, sans-serif; font-size: 12px; text-align: justify; width: 92%; margin: auto; border: 1px solid #aaa; padding: 1em;"> | ||
| + | == Module 1: Boolean Algebra & CMOS logic structures == | ||
| + | <span style="color:orange"> UNDER CONSTRUCTION </span> | ||
| + | *[[ECE270 Slecture Wayner Digital System Design Objectives Module 1|Objectives and Outcomes]] | ||
| + | *[[ECE270 Fall 2013 Module 1 Slecture 1|Converting integers to binary]] | ||
| + | *[[ECE270 Fall 2013 Module 1 Slecture 2|Using MOSFETS as logic gates]] | ||
| + | *[[ECE270 Fall 2013 Module 1 Slecture 3|Basics of Open Drain NAND gates]] | ||
| − | + | ([https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod1_LS_IMPACT_2013.pdf Original Notes by Prof. Meyer]) | |
| − | + | </div> | |
| − | + | <br> | |
| − | + | <div style="font-family: Verdana, sans-serif; font-size: 12px; text-align: justify; width: 92%; margin: auto; border: 1px solid #aaa; padding: 1em;"> | |
| − | + | ||
== Module 2: Combinational Logic Circuits & Introduction to ABEL == | == Module 2: Combinational Logic Circuits & Introduction to ABEL == | ||
| − | *[https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod2_LS_IMPACT_2013.pdf Original | + | <span style="color:orange"> TO BE DONE LATER </span> |
| − | : | + | *[[ECE270 Slecture Wayner Digital System Design Objectives Module 2|Objectives and Outcomes]] |
| + | |||
| + | ([https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod2_LS_IMPACT_2013.pdf Original Notes by Prof. Meyer]) | ||
| + | |||
| + | </div> | ||
| + | <br> | ||
| + | <div style="font-family: Verdana, sans-serif; font-size: 12px; text-align: justify; width: 92%; margin: auto; border: 1px solid #aaa; padding: 1em;"> | ||
== Module 3: Sequential Logic Circuits == | == Module 3: Sequential Logic Circuits == | ||
| − | :[https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod3_LS_IMPACT_2013.pdf Original | + | <span style="color:orange"> TO BE DONE LATER </span> |
| + | *[[ECE270 Slecture Wayner Digital System Design Objectives Module 3|Objectives and Outcomes]] | ||
| + | |||
| + | ([https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod3_LS_IMPACT_2013.pdf Original Notes by Prof. Meyer]) | ||
| + | </div> | ||
| + | <br> | ||
| + | <div style="font-family: Verdana, sans-serif; font-size: 12px; text-align: justify; width: 92%; margin: auto; border: 1px solid #aaa; padding: 1em;"> | ||
== Module 4: Computer Functional Block & Arithmetic Logic Unit == | == Module 4: Computer Functional Block & Arithmetic Logic Unit == | ||
| − | :[ | + | <span style="color:orange"> TO BE DONE LATER </span> |
| − | + | *[[ECE270 Slecture Wayner Digital System Design Objectives Module 4|Objectives and Outcomes]] | |
| − | [ | + | ([https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod4_LS_IMPACT_2013.pdf Original Notes by Prof. Meyer]) |
| + | </div> | ||
| + | <br> | ||
| + | ---- | ||
| − | [[ | + | [[2014 Spring ECE 270 Brown|Go to ECE 270 Homepage]] |
Latest revision as of 16:38, 2 April 2014
The Meyer Lectures on Digital Systems Design
© 2013
Contents
Foreword by Robert Wayner
Module 1: Boolean Algebra & CMOS logic structures
UNDER CONSTRUCTION
Module 2: Combinational Logic Circuits & Introduction to ABEL
TO BE DONE LATER
Module 3: Sequential Logic Circuits
TO BE DONE LATER
Module 4: Computer Functional Block & Arithmetic Logic Unit
TO BE DONE LATER
