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== Module 2: Combinational Logic Circuits & Introduction to ABEL == | == Module 2: Combinational Logic Circuits & Introduction to ABEL == | ||
<span style="color:orange"> UNDER CONSTRUCTION </span> | <span style="color:orange"> UNDER CONSTRUCTION </span> | ||
| − | *Objectives and Outcomes | + | *[[ECE270 Slecture Wayner Digital System Design Objectives Module 2|Objectives and Outcomes]] |
*[[ECE270 Fall 2013 Module 2 Slecture 1|Karnaugh Map techniques]] | *[[ECE270 Fall 2013 Module 2 Slecture 1|Karnaugh Map techniques]] | ||
| Line 41: | Line 41: | ||
== Module 3: Sequential Logic Circuits == | == Module 3: Sequential Logic Circuits == | ||
<span style="color:orange"> UNDER CONSTRUCTION </span> | <span style="color:orange"> UNDER CONSTRUCTION </span> | ||
| − | *Objectives and Outcomes | + | *[[ECE270 Slecture Wayner Digital System Design Objectives Module 3|Objectives and Outcomes]] |
([https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod3_LS_IMPACT_2013.pdf Original Notes by Prof. Meyer]) | ([https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod3_LS_IMPACT_2013.pdf Original Notes by Prof. Meyer]) | ||
| Line 49: | Line 49: | ||
== Module 4: Computer Functional Block & Arithmetic Logic Unit == | == Module 4: Computer Functional Block & Arithmetic Logic Unit == | ||
<span style="color:orange"> UNDER CONSTRUCTION </span> | <span style="color:orange"> UNDER CONSTRUCTION </span> | ||
| − | *Objectives and Outcomes | + | *[[ECE270 Slecture Wayner Digital System Design Objectives Module 4|Objectives and Outcomes]] |
Revision as of 08:46, 21 August 2013
The Meyer Lectures on Digital Systems Design
© 2013
Contents
Foreword by Robert Wayner
Module 1: Boolean Algebra & CMOS logic structures
Module 2: Combinational Logic Circuits & Introduction to ABEL
UNDER CONSTRUCTION
Module 3: Sequential Logic Circuits
UNDER CONSTRUCTION
Module 4: Computer Functional Block & Arithmetic Logic Unit
UNDER CONSTRUCTION
