Line 19: Line 19:
 
<div style="font-family: Verdana, sans-serif; font-size: 12px; text-align: justify; width: 92%; margin: auto; border: 1px solid #aaa; padding: 1em;">
 
<div style="font-family: Verdana, sans-serif; font-size: 12px; text-align: justify; width: 92%; margin: auto; border: 1px solid #aaa; padding: 1em;">
 
== Module 1: Boolean Algebra &amp; CMOS logic structures  ==
 
== Module 1: Boolean Algebra &amp; CMOS logic structures  ==
 +
*[[ECE270 Slecture Wayner Digital System Design Objectives|Objectives and Outcomes]]
 
*[https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod1_LS_IMPACT_2013.pdf Original Lecture Summary Notes for Module 1]
 
*[https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod1_LS_IMPACT_2013.pdf Original Lecture Summary Notes for Module 1]
 
**[[ECE270 Fall 2013 Module 1 Slecture 1|Converting integers to binary]]
 
**[[ECE270 Fall 2013 Module 1 Slecture 1|Converting integers to binary]]

Revision as of 06:01, 23 July 2013


The Brown-Meyer Lectures on Digital Systems Design

Slectures by Robert Wayner

© 2013




Module 2: Combinational Logic Circuits & Introduction to ABEL

UNDER CONSTRUCTION


Module 3: Sequential Logic Circuits

UNDER CONSTRUCTION


Module 4: Computer Functional Block & Arithmetic Logic Unit

UNDER CONSTRUCTION



Go to ECE 270 Homepage

Alumni Liaison

Questions/answers with a recent ECE grad

Ryne Rayburn