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| − | == [[ECE270 Fall 2013 | + | == [[ECE270 Fall 2013 intro Slecture Digital System Design|Foreword by Robert Wayner]]== |
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== Module 1: Boolean Algebra & CMOS logic structures == | == Module 1: Boolean Algebra & CMOS logic structures == | ||
*[https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod1_LS_IMPACT_2013.pdf Original Lecture Summary Notes for Module 1] | *[https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod1_LS_IMPACT_2013.pdf Original Lecture Summary Notes for Module 1] | ||
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**[[ECE270 Fall 2013 Module 1 Slecture 2|Using MOSFETS as logic gates]] | **[[ECE270 Fall 2013 Module 1 Slecture 2|Using MOSFETS as logic gates]] | ||
**[[ECE270 Fall 2013 Module 1 Slecture 3|Basics of Open Drain NAND gates]] | **[[ECE270 Fall 2013 Module 1 Slecture 3|Basics of Open Drain NAND gates]] | ||
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== Module 2: Combinational Logic Circuits & Introduction to ABEL == | == Module 2: Combinational Logic Circuits & Introduction to ABEL == | ||
<span style="color:orange"> UNDER CONSTRUCTION </span> | <span style="color:orange"> UNDER CONSTRUCTION </span> | ||
*[https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod2_LS_IMPACT_2013.pdf Original Lecture Summary Notes for Module 2] | *[https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod2_LS_IMPACT_2013.pdf Original Lecture Summary Notes for Module 2] | ||
**[[ECE270 Fall 2013 Module 2 Slecture 1|Karnaugh Map techniques]] | **[[ECE270 Fall 2013 Module 2 Slecture 1|Karnaugh Map techniques]] | ||
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== Module 3: Sequential Logic Circuits == | == Module 3: Sequential Logic Circuits == | ||
<span style="color:orange"> UNDER CONSTRUCTION </span> | <span style="color:orange"> UNDER CONSTRUCTION </span> | ||
*[https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod3_LS_IMPACT_2013.pdf Original Lecture Summary Notes for Module 3] | *[https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod3_LS_IMPACT_2013.pdf Original Lecture Summary Notes for Module 3] | ||
| + | </div> | ||
| + | <br> | ||
| + | <div style="font-family: Verdana, sans-serif; font-size: 12px; text-align: justify; width: 92%; margin: auto; border: 1px solid #aaa; padding: 1em;"> | ||
== Module 4: Computer Functional Block & Arithmetic Logic Unit == | == Module 4: Computer Functional Block & Arithmetic Logic Unit == | ||
<span style="color:orange"> UNDER CONSTRUCTION </span> | <span style="color:orange"> UNDER CONSTRUCTION </span> | ||
*[https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod4_LS_IMPACT_2013.pdf Original Lecture Summary Notes for Module 4] | *[https://engineering.purdue.edu/ece270/Notes/PDF/2-Mod4_LS_IMPACT_2013.pdf Original Lecture Summary Notes for Module 4] | ||
| + | </div> | ||
| + | <br> | ||
---- | ---- | ||
| − | [[2013 Fall ECE 270 Brown| | + | [[2013 Fall ECE 270 Brown|Go to ECE 270 Homepage]] |
[[Category:ECE270]] [[Category:Lecture_notes]] [[Category:Slecture]] | [[Category:ECE270]] [[Category:Lecture_notes]] [[Category:Slecture]] | ||
Revision as of 05:50, 23 July 2013
The Brown-Meyer Lectures on Digital Systems Design
© 2013
Contents
Foreword by Robert Wayner
Module 1: Boolean Algebra & CMOS logic structures
Module 2: Combinational Logic Circuits & Introduction to ABEL
UNDER CONSTRUCTION
Module 4: Computer Functional Block & Arithmetic Logic Unit
UNDER CONSTRUCTION
